The SLP74AHC595 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3- state outputs.
Separate clocks are provided for both the shift and storage registers. Data is shifted on the positive-going transitions of the shift register clock input (SHCLK). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCLK). If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable (OE) input is LOW. When the output-enable (OE) input is high, all outputs except Q7S are in the high-impedance state.
Operating range: 2V to 5.5V VCC
8-bit serial-in, parallel-out shift
Inputs accepts voltages higher than VCC
CMOS input levels
ESD protection:
HBM exceeds 2000V
CDM exceeds 1000V
Latch-up performance exceeds 100mA
Specified from -40°C to +85°C and from -40°C to +125°C
| Product Name | Package form | Marking | Hazardous Substance Control | Packing Type | Remarks |
|---|---|---|---|---|---|
| SLP74AHC595JS | TSSOP-16-225-0.65 | AHC595 | Halogen free | Tube | |
| SLP74AHC595JSTR | TSSOP-16-225-0.65 | AHC595 | Halogen free | Tape&Reel |
Fig.1 Block diagram
